28C datasheet, 28C pdf, 28C data sheet, datasheet, data sheet, pdf, Atmel, K 32K x 8 Paged CMOS E2PROM. 28C Microchip. K (32K x 8) CMOS Electrically Erasable PROM. PIN CONFIGURATION. Top View. A 1 A7. A A *NC. Vcc. WE. [1]. A2. 5 WE. A dimensions section on page 14 of this data sheet. ORDERING INFORMATION. PLCC−32 . 28C− 28C− Units. Min. Max. Min. Max. tRC.

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Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

Hardware and Software Data Protection. After setting SDP, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. When enabled, the software data protection SDPwill prevent inadvertent writes. It should be noted, that once protected the host may still perform a byte or page write to the AT28C Page Write Cycle Time: Hardware features protect against inadvertent writes to the AT28C in the follow- ing ways: All Output Voltages with Respect to Ground All bytes dur- ing a page write operation must reside on the same page as defined by the state of the A6 – A14 inputs.

The device contains a byte page register to allow writ- ing of up to bytes simultaneously.

Its K of memory is organized as 32, words by 8 bits. The A0 to A5 inputs are used to specify which bytes within the page are to be written. DATA Polling may begin at anytime during the write cycle.


28C – 28C K ns Parallel EEPROM Technical Data

Fast Write Cycle Times. The data is latched by the first rising edge of CE or WE. The entire device can be erased using a 6-byte software code. Search field Part name Part description.

X can be V. An optional software data protection mechanism is available to guard against inad- vertent writes.

28C 데이터시트(PDF) – Xicor Inc.

The outputs are put in the high impedance state when either CE or OE is high. For each WE high to low transition during the page write operation, A6 – A14 must be the same. Once a byte write has been started it will automatically time itself to completion. The bytes may be loaded in any order and may be altered within the same load period. After writing the 3-byte command sequence and after t. When CE and Datasheef are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs.

Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. PROM for device identification or tracking. Please see Soft- ware Chip Erase application note for details. A software controlled data protection feature has been implemented on the AT28C PROM memory are available to the user for device.

SDP is enabled by the host system issuing a series of three write commands; three specific bytes of darasheet are written to three specific addresses refer to Software Data Protection Algorithm. The data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data in either a byte or page write operation.


Once a programming operation has been initiated and for the duration of t. CE to Output Delay.

28C256 – 28C256 256K 250ns Parallel EEPROM Technical Data

Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. OE to Output Delay.

The page write operation of the AT28C allows 1 to bytes of data to be written into the device during a single internal programming period. The device also includes an extra bytes of E. No data will be written to the device; however, for the duration of t. This is done by pre- ceding the data to be written by the same 3-byte command sequence used to enable SDP.

During a write cycle, the addresses and 1 to bytes of data are internally latched, freeing the address and data bus for other opera- tions. Once the end of a write cycle has been detected a new access for a read or write can begin. Address to Output Delay. Input Test Waveforms and Measurement Level. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied.

Stresses beyond those listed under “Absolute Maxi. CE may be delayed up to t. Fast Read Access Time – ns.